DESIGN AND REALIZATION OF A 50 MFIPS FUZZY PROCESSOR IN 1.0 μm CMOS VLSI TECHNOLOGY
نویسندگان
چکیده
This paper deals with two problems: the first concerns the design of the HW architecture of a high speed Fuzzy Processor that works at 50 Mega Fuzzy Inference per Second (MFIPS). It has eight 7 bit inputs and one 7 bit output. It is foreseen to apply it as a part of the trigger device in HEP (High Energy Physics) experiments, the second one concerns the 1.0 μm CMOS VLSI design of the fuzzification and inference process and the defuzzifier circuits. These circuits have already been realized and tested. The design has been done using Cadence SW tools we obtained via
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